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| |
 | Dally, William J., and Poulton, John W., "Digital Systems
Engineering", Cambridge University
Press, 1998.
Digital
Systems Engineering Home Page |
| W.J. Dally, M.-J. E. Lee, F.-T. R. An, J. Poulton, and S. Tell, "High Performance Electrical
Signaling", MPPOI98, 1998.
[postscript, 749KB] [zip'ed postscript, 277KB]
[PDF,
110KB] |
| W.J. Dally, M.-J. E. Lee, F.-T. R. An, J. Poulton, "A Small Low-Power High-Speed
Link", IEEE/LEOS Ninth Workshop on
Interconnections within High-Speed Digital Systems, May 18, 1998.
[Slides, postcript, 5.6MB] [zip'ed postcript 2.8MB]
[PDF,
537KB] |
| W.J. Dally, J. Poulton, and S. Tell, "Multi-gigabit signaling with
CMOS", IEEE/LEOS Eighth Workshop on
Interconnections within High-Speed Digital Systems, May 12, 1997.
[Slides, postscript, 9MB] [zip'ed postscript,
785KB] [PDF, 181KB] |
| W.J. Dally, J. Poulton, and S. Tell, "A Tracking Clock Recovery Receiver
for 4 Gb/s signaling," IEEE Micro Jan/Feb 1998, pp15-26. This is a condensed version
of the Hot Interconnects '97 presentation. |
| W.J. Dally, J. Poulton, and S. Tell, "A Tracking Clock Recovery Receiver
for 4 Gb/s signaling." Presented at Hot Interconnects '97, August 21-23, 1997, Palo
Alto, CA.
[postcript, 2419KB] [zip'ed postcript, 1189KB]
[PDF, 326KB] |
| W.J. Dally, J. Poulton, "Transmitter Equalization for 4 Gb/s
signaling," IEEE Micro Jan/Feb 1997, pp48-56.
[postcript, 908KB] [zip'ed postcript, 241KB]
[PDF,
170KB] |
| W.J. Dally, J. Poulton, "Transmitter Equalization for 4 Gb/s
signaling," Hot Interconnects '96. This paper was slightly revised
and reprinted by IEEE Micro as the preceding item.
[postcript, 747KB] [zip'ed postcript, 201KB]
[PDF,
119KB] |
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